The present invention relates generally to the field of semiconductor manufacturing and more particularly to optimizing circuit design.
Multiple patterning (or multi-patterning) is a class of technologies for manufacturing integrated circuits (ICs), developed for photolithography to enhance the feature density. There are several types of multiple patterning techniques including self-aligned double patterning (SADP), Litho-Etch-Litho-Etch (LELE) and self-aligned quadruple patterning (SAQP) methods.
Multiple patterning entails the use of many processing steps to form a patterned layer, where conventionally, single patterning, only one lithographic exposure, one etch sequence and one deposition sequence would be adequate. The premise is that a single lithographic exposure may not be enough to provide sufficient resolution. Therefore, additional exposures would be needed, or otherwise, the positioning patterns using etched feature sidewalls (using spacers) would be necessary.
Multi-patterning technology has its own process and design trade-offs. Specifically, designs with moving from one technology node to another bears the increase in cost against the improvements in area and performance. Without multi-patterning, IC designers struggle to design at 14 nm feature size or below, which limits the opportunity to take advantage of design area and performance scaling. Multi-patterning affects almost all aspects of design and manufacturing. For example, in physical design it adds additional design rule constraints and constrains cell placement and routing depending on cell architecture. In another example, for electrical design it adds additional parasitic variability to consider in timing analysis. In a further example, for design for manufacturability (DFM), it adds additional requirements for fill and lithographic checking. In manufacturing, it adds additional masks, process steps and increases stepper utilization. All of these trade-offs increase complexity and have higher associated cost.
Furthermore, additional optimization in SADP may require scrutiny in the physical design tools in order to access Standard Cell (SC) Input/Output (I/O) pins within a more congested areas. However, there are complex design rules that restricts human-driven layout design from achieving better yield and throughput. Hence, a means to automate a standard cell layout design is required for 14 nm technologies and below. SADP, in particular, is an ideal candidate for lower layer metallization with regular patterns at the 10 nm technology node, due to ideal overlay and Line Edge Roughness (LER) control compared to LELE. Some circuit design systems have additional but redundant vias to enhance manufacturing yields wherein yield is a statistical quantity defining number of operational chips over the whole ensemble. However, these poorly located vias may be too close to an interconnect which may lead to electrical shorting through via bleeding, i.e., a laterally elongated via touching a neighboring interconnect, or electrical opens in the form of via voiding, i.e., a partially filled via that does not conduct well and is highly resistive. These usually can be fixed by extending lineends beyond a via, thus increasing lineend to via overlap distance. In another example, some designs may contain complex cuts for polygon and lineend that are counterproductive during the manufacturing process. Below are some definitions that will be utilized throughout an embodiment of the present invention.
A polygon is a layer consisting of pre-determined patterns with a pre-defined number of vertices. A lineend or line-end is the end point of the target “line” that can be defined by a cut. An interconnect is conductor (typically metal) line connecting elements of an integrated circuit. A via is a vertical electrical connection. A cut or cutmask is a mask to define lineends.
Accordingly, there exists a need to implement a better circuit DFM optimization within 14 nm technologies and beyond. In particular, the disclosed embodiment of the present invention targets lineend to via overlap optimization.